The advent of physical AI promises to deliver autonomous platforms that are more able to operate in the changing world around them. Decisions made by the physical AI models need to be enacted by robots that move in a safe, precise manner. With physical AI models using reinforcement learning to understand the world, the next-generation of control-loop processors is needed to drive intelligence into action. Control loops drive the precise use of actuators and motors for smooth, efficient movement, conversion, and action.
Event-driven low-latency platforms can be applied to a wide range of applications, such as motor control, electric vehicle charging, and the battery management systems of autonomous devices from warehouse robots to agricultural tractors and electric or hybrid vehicles. The markets deliver the following benefits:
- Motor Control: Smaller, lighter motors, decreasing cost and weight. Faster motors with more precise control of torque, speed, and position, for increased performance and efficiency.
- Digital Power Conversion: Increased efficiency and power density including SiC and GaN wide band gap semiconductors.
- Battery Management: Precise control of “State of Charge” and “State of Health” for more accurate and safe battery state algorithms.
As the microcontroller (MCU) market has evolved, a real-time MCU problem has developed. When I look at the 32-bit MCU processor market, I see two groups of existing solutions. The first group consists of legacy proprietary architecture processors that might meet real-time performance but are generally difficult to program. That is, embedded programmers may have to learn the processor architecture and program in handwritten assembly to get performance entitlement. Additionally, since the architecture is proprietary, customers often become dependent on the processor vendor for everything including compiler, toolchain, debug, etc.
To solve this problem, MIPS developed the M8500 real-time compute subsystems product line, offering low-latency, functionally safe, reliable processing for a variety of applications.
The MIPS M8500 is a unique new compute solution that solves the real-time MCU problem at the architecture level. With determinism, safety, and real-time performance features built into its DNA, the M8500 delivers low-latency control loops. Engineered on the foundation of RISC-V, this real-time performance can be achieved on a general-purpose programming model with no handwritten assembly and no deep processor architecture knowledge necessary. Developers can compile C-code with their existing tools and instantly achieve the desired performance entitlement. This enables software teams to focus on the application layer code where differentiation is needed, instead of wasting time on low-level firmware optimization. The M8500 already has wide compiler, toolchain, debug, and trace support out-of-box with 100% RISC-V compliance. Adopting RISC-V open instruction set architecture (ISA) means that customers don’t have to worry about vendor lock-in, continuing to use existing workflows.
Availability of the MIPS M8500 real-time compute subsystem for lead customer evaluation is expected mid-year 2025, with evaluation boards in 4Q25 and reference silicon availability in 1H26. 2025 from March 11th – 13th, in Nuremburg, Germany (Hall 5 – Booth #136). To request a meeting, please contact us here: MIPS.com/events
