Former SiFive Leaders to Help Drive IP Innovation and Market Penetration
SAN JOSE, CA – January 03, 2024 – MIPS, a leading developer of high- performance RISC-V compute IP, today announced the addition of two semiconductor industry veterans to its leadership team. Drew Barbier joins the company as VP of Products and Brad Burgess has been named Chief Architect. Both executives join the MIPS Executive Leadership team.
“I am very excited to have both Drew and Brad join the team at this crucial time in MIPS’ journey as we embark on a new path for the company,” said Sameer Wasson, CEO of MIPS. “Given Drew’s and Brad’s proven track records in the semiconductor IP space with a recent focus on RISC-V, I am confident in their abilities to help drive IP innovation and penetration into new markets.”
Mr. Barbier has 15+ years of semiconductor and IP product experience, most recently serving for more than six years at SiFive as the Senior Director of Product Management. Prior to SiFive, Mr. Barbier held technical and product management roles for companies including Faraday Technology Corporation, Arm and Analog Devices.
As the new VP of Products, Mr. Barbier will oversee and further drive MIPS’ product roadmap as the company continues to expand its footprint in the automotive, cloud and embedded markets.
“I am excited to join MIPS and as the company continues to accelerate RISC-V innovation and expand into new markets,” said Mr. Barbier. “The need for RISC-V has never been greater, as heterogeneous compute requirements become increasingly complex. I am looking forward to working with the entire team to deliver new high-density compute solutions that create value and differentiation to MIPS customers.”
Mr. Burgess brings to MIPS more than three decades of semiconductor and RISC-V industry experience, with a broad design and CPU architecture background. Prior to joining the company, Mr. Burgess served as SiFive’s Chief CPU Architect. Over time, he has delivered a number of high-volume products in numerous instruction sets including RISC-V, ARM, 68K, PowerPC and x86.
As MIPS’ Chief Architect, Mr. Burgess will be responsible for technology architecture and development of all new key roadmap product designs at MIPS.
“MIPS is well positioned to address the increasingly complex compute needs of companies who are looking to innovate and design without constraints,” said Mr. Burgess. “I am thrilled to join the expanding MIPS team and leverage my expertise to help drive company growth at a time when RISC-V is experiencing tremendous momentum and adoption.”
In addition to growing its executive team, MIPS is expanding with new offices in both Dallas and Austin, TX while continuing to grow in the company’s existing locations in San Jose, CA and Bangalore, India. As a leading IP developer with deep technical expertise, MIPS continues to accelerate RISC-V innovation at a time when chipmakers are searching for more flexible, scalable and faster-time-to-market solutions.
MIPS at CES 2024
Members of the new MIPS’ executive leadership team will be available to meet with journalists, analysts, customers and partners January 9 – 12, 2024, at the Consumer Electronics Show (CES). Throughout the week, MIPS will have live demos showcasing real-time system deployments in its private hospitality suite at the Venetian hotel. The company will also host an executive meet-and-greet event on Wednesday, Jan. 10 from 10:15 a.m. – 11:15 a.m. To request a meeting, complete this form.
For more information about the MIPS leadership team please visit https://mips.com/leadership/
About MIPS
MIPS is a leading developer of high-performance RISC-V compute IP for high-end automotive, computing and communications applications. With its deep engineering expertise built over 35 years and billions of MIPS-based chips shipped to date, today the company is accelerating RISC-V innovation for a new era of compute. The company’s proven solutions are uniquely configurable, enabling semiconductor companies to hit exacting performance and power requirements and differentiate their devices.
