Do you need more compute elements? Do you need more memory? Do you need more cache? Last week we announced the MIPS P8700, the industry’s first AI-enabled RISC-V automotive CPU for ADAS and autonomous vehicles. The MIPS P8700 gives you the freedom to choose how to solve your problem.
How is scalability optimized?
The MIPS P8700 scalability starts with the core. Your core can choose one or two high performance, out-of-order compute engines known as harts within a single core. That same core can choose 32KB or 64KB L1 instruction cache and 32KB or 64KB L1 data cache for the two harts to share.
You can further enhance the core with L2 cache from 256KB to 2MB. At this L2 level you can also keep building with multiple cores in a single cluster. Add up to 5 more cores to give a cluster of 6 cores and 12 harts of compute with a shared L2 cache.
The next degree of freedom is to increase total computation and all levels of cache by expanding the number of clusters. With the use of a coherent NoC, you can expand up to 64 clusters. This allows you to increase your total compute capacity to 768 harts, your L1 caches to 48 MB, and your L2 caches to 128 MB.
Although the maximums are shown above, the freedom comes from your ability to tailor your solution. If you want more compute engines, you can choose more cores and harts and smaller cache sizes to optimize your area. Similarly, if your sweet spot is more data, you can put larger L1 cache and decide how many cores to share each cluster L2.
Scalability means you are in control. You can choose your system configuration with a very wide range of computation, cache memory – L1, L2 levels, and overall system memory capacity.
Learn more in our MIPS RISC-V P8700 Processor IP product brief and data sheet. Available for download.
