I8500 Series
Efficient Throughput
- Superscalar 3-Wide, 9-stage, in-order pipeline
- Efficient data-centric processing
- 4-Way Simultaneous multi-threading (SMT), with no switching overhead
- Low latency and deterministic data access
- RISC-V Compliant ISA
- RVB23
- CMO Extension, Hardware virtualization (H Extension)
- MIPS Defined Instructions (MDI)—Cache and TLB management, Performance enhancements and DVM (Distributed Virtual Memory) support
- Optional up to 1MB Data and Instruction ScratchPad RAMs (DSPRAM, ISPRAM) for real-time, low-latency applications
Coherence Manager
- Support for up to 8 coherent initiators comprising of either MIPS RISC-V Processors or 3rd party accelerators
- Cluster Level-2 Cache L2$ up to 2MB
- Hardware pre-fetch
- System interface(s):
- ACE or AXI: Configurable 128/256/512-bit system bus
- Optional: Non-coherent periphery busses (up to 4 ports)
A specialized data orchestration processor for high-speed, rule-based data filtering, prioritization, and movement
- Multithreaded Efficiency
- Programmable Pipelines
- Scalable Enablement
- Physical AI Ready
Design and Innovate with MIPS Today
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