I-Class I6500 Multiprocessor Core

Like the I6400 IP core family before it, the foundation of the I6500 family is a multi-threaded superscalar CPU core which, in a single multi-core cluster, can utilize up to six cores. As the basis for its “heterogeneous inside” capabilities, each core in the cluster can now be individually configured as part of silicon design to optimize and align the performance, area and power of the total solution to application requirements. This includes varying the number of hardware threads, the size of each L1 cache, as well as optional inclusion of a SIMD/FPU processing unit.

Data ScratchPad RAM (SPRAM) per core, up to four AXI ports for low-latency peripherals or cluster-level SPRAM, and inter-thread communications (ITC) support are available as options. These features support both deterministic, low-latency operation and fast path messaging in embedded systems, and implementations of high-performance networking/data processing applications operating as a complement to the standard cached memory system.

The combination of simultaneous multi-threading with hardware virtualization in the I6500 processor enables multiple execution environments to run simultaneously, isolated from each other, with zero context switch overhead.

The operating frequency and voltage can also be varied per CPU, enabling dynamic runtime optimization of performance and power consumption, or even silicon design optimization of cores to different performance, area, and power consumption attributes within a single cluster. An example of such a configuration, as well as some of the features described above, can be seen in the figure above.

One of the key capabilities of the I6500 family is the support for multi-cluster and “heterogeneous outside” compute scalability. The primary system interface for an I6500 cluster is ACE compatible. As such, in conjunction with popular third party SoC coherent interconnect/fabric alternatives, the I6500 family can be used in “many core” implementations of up to 64 clusters, or >1500 processing elements (up to four threads/core, up to six cores/cluster, up to 64 clusters). MIPS also provides multi-cluster subsystems as one of the extended licensing options.

“Heterogeneous outside” features of the I6500 family encompass capabilities for mixing the multi-cluster CPU functionality that is the foundation of this technology, and adding in the ability to work coherently with other processing/compute elements. This includes the ability to support coherent multi-processing with ACE compatible co-processors.

The capabilities of the I6500 family extend even further on the “heterogeneous outside” framework through a unique feature supporting the build of “accelerator only” cluster(s). A single cluster of the I6500 family platform can actually be configured for having up to eight IO coherence units (IOCUs) connected together, with no CPU in the cluster.

Custom-designed or third party functional accelerators can be connected via standard AXI4 interface to these IOCU ports, providing very localized and concentrated compute resources for specific tasks or applications. Such a configuration provides benefits to a cluster of functional accelerators by utilizing a localized, shared low latency L2 cache among the accelerator units. It concentrates the processing and traffic of the accelerators and the CPUs into separate clusters.

In this way there is less competing traffic and bandwidth allocation to the respective L2 cache memories for each processing cluster –all the while maintaining memory coherency between the respective L2 caches. And this capability provides both a standards-based mechanism for creating clusters of accelerators, and more localized, lower latency communication to the CPUs than implementing the accelerators further out on a coherent NoC fabric.