microMIPS Architecture

Designed for microcontrollers and other small footprint embedded devices, microMIPS is a code compression instruction set architecture (ISA) that offers 32-bit performance with 16-bit code size for most instructions. It maintains 98% of MIPS32 performance while reducing code size by up to 25%, translating to significant silicon cost savings. With smaller memory accesses and efficient use of the instruction cache, microMIPS also helps to reduce system power consumption.

The microMIPS ISA combines recoded and new 16- and 32-bit instructions to achieve an ideal balance of performance and code density. It incorporates all MIPS32 instructions and architecture modules including MIPS DSP and MIPS MT, as well as new instructions for advanced code size reduction. The microMIPS ISA is backward compatible, enabling reuse of optimized MIPS microarchitecture.

microMIPS is supported in releases r3, r5 and r6 of the MIPS architecture. It is implemented in MIPS CPUs including the M14K, microAptiv, and the Warrior M51xx and M62xx series of cores. Compiler support is included in the Codescape development tools.