MIPS proAptiv Processor Core

MIPS proAptiv is a family of microprocessor IP cores designed to deliver the compelling top-line performance required for connected consumer electronics including connected TVs and set-top boxes and high-performance compute in embedded applications.

proAptiv CPUs are based on a wide issue, deeply out-of-order (OoO) implementation of the MIPS32 architecture, and are available in single and multi-core product versions supporting up to six cores.

The proAptiv family leverages an advanced microarchitecture, an upgraded floating point unit (FPU), and an enhanced multi-core interconnect to deliver a major leap forward in performance over the previous generation of MIPS Classic CPU IP cores, while implementing in nearly the half the size of competing cores in the same process node.


The MIPS interAptiv CPU utilizes the second generation Coherence Manager (CM2) interconnect, which has an integrated L2 cache. The CM2 improves multi-core performance by simultaneously reducing latency and increasing bandwidth. The CM2 supports up to four interAptiv CPUs or eight virtual processors in a single, fully coherent, multi-processor system.

As an increasing amount of data is stored and transported to and from a variety of embedded client devices and storage infrastructure equipment, data reliability is a growing requirement. The interAptiv CPU, which has Error Correction Code (ECC) support on data memories, makes it a great fit for higher reliability applications such as RAID storage and automotive driver assistance.

The interAptiv CPU, with its robust ability to control power at both the cluster and core levels, makes power management a snap for SoC designers.

  • 32-bit MIPS32® Release 3 Instruction Set Architecture with up to six cores
  • High-performance, 16-stage, multiissue out-of-order (OoO) pipeline
  • I/D L1 cache sizes of 32KB or 64KB each, 4-way set associative
  • Programmable Memory Management Unit (MMU)
  • MIPS DSP Module, version 2
  • Optional 2nd gen hi-performance dual-issue Floating Point Unit (FPU)
  • Advanced power management at base core and multi-core cluster levels
  • EJTAG/PDtrace debug
  • Superscalar, OoO processor available in application-optimized single and multicore versions
  • Sophisticated branch prediction for performance on modern software workloads
  • Load/Store bonding for optimum data movement performance
  • EVA (Enhanced Virtual Addressing) – programmable virtual address map for optimal use of 32-bit address space
  • Industry leading benchmark and real world performance without an increase in area and power
  • Broad software and ecosystem support and mature toolchain
  • Available as synthesizable IP, for implementation in any process node, with standard cells and memories
  • Connected DTV/STB
  • Networking
  • Automotive infotainment
  • High-performance compute

Baseline Specifications

Target TSMC 28HPM
Frequency 1 GHz – 2+ GHz*
CoreMark/MHz (per core) >5
Total CoreMark @ 1.5GHz >7500 per core
DMIPS/MHz (per core) 3.5
Total DMIPS @ 1.5GHz >5250 per core

Frequencies indicated are for fully floorplanned dual core implementation, ranging from 12T SVt area-optimized in worst case silicon corner, to 12T MVt speed-optimized typical corner silicon.

Each base core configuration:
  • 32KB Data/Inst L1 caches with parity, BIST
  • New high-speed FPU
  • Fully-featured MMU, using multi-level TLB
    (I/D uTLBs + 128 entry VTLB + 1024 entry FTLB)
  • PDtrace™ debug
Multi-core cluster configuration:
  • Dual fully-configured proAptiv cores per above
  • Coherence Manager + integrated 1MB L2$ w/ECC
  • One hardware IO Coherence Unit (IOCU) port
  • One hardware IO Coherence Unit (IOCU) port
Cluster level PDtrace Implementation libraries/parameters – speed optimized, based on:
  • TSMC 28HPM 12T standard cells + Synopsys memories
  • Worst case, slow-slow corner silicon (zero temp, WCZ)
    with 10% OCV + 25ps clock jitter margins, except where noted at typical silicon.