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microMIPS™

microMIPS™ Instruction Set Architecture

microMIPS™ is a high performance code compression technology that combines optimized 16- and 32-bit instructions in a single, unified Instruction Set Architecture (ISA). It supports both MIPS32® and MIPS64® Release 2 architectures, providing uncompromised performance and a high level of code density by incorporating a combination of variable length re-encoding MIPS instruction set and additional code-size optimized 16- and 32-bit instructions.

As a complete ISA, microMIPS can operate standalone or in co-existence with the legacy-compatible MIPS32 instruction decoder, allowing programs to intermix 16- and 32-bit code without having to switch modes. The smaller code footprint of microMIPS leads to better cache utilization and lower fetch bandwidth, helping to improve performance and reduce power consumption.

microMIPS includes all MIPS ASE instructions and supports the CorExtend™/UDI interface. microMIPS software and system development is supported by a comprehensive set of hardware and software tools provided by MIPS Technologies, as well as an ecosystem of third party partners. microMIPS is initially implemented in the new M14K™and M14Kc™processor cores.

  • A code compression ISA that maintains 98% of MIPS32 performance while reducing code size by 35%, translating to significant silicon cost savings
  • Developed in both MIPS32 and MIPS64 architecture-compatible formats—the unified ISA has 16- and 32-bit opcodes in the MIPS32 version and additional 48-bit opcodes in the MIPS64 version
  • Optimized opcode and operand field definitions based on statistical analysis of a wide range of application software, middleware, RTOS and Linux kernel
  • MIPS assembly source code level and ABI compatible
  • Maintains MIPS' proven compiler efficiency in code generation
  • Supports all existing MIPS32 and MIPS64 instructions
  • Designed around a variable length re-encoding scheme
  • 15 new 32-bit and 39 new 16-bit instructions
  • Frequent MIPS32 instructions and macros re-encoded as16-bit
  • Register and immediate values are reduced in size for 16-bit instructions
  • Opcode format split into 6-bit major opcode and variable-length minor opcode
  • Covers all major, most frequently used instruction types including load/store multiple
  • Branch/word targets are half-word aligned
  • Maintained branch and jump delay slots
  • Less frequent load/stores have smaller offsets to maximize code size reduction
  • Fine tuned register allocation algorithm in the compiler
  • Supported by Codesourcery Sourcery G++ GNU toolchain
  • System debug and development support provided by MIPS® Navigator Integrated Component Suite (ICS) and System Navigator™ probe


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MIPS32® Architecture Reference Manual Volume IV-g: microMIPS™

MIPS64® Architecture Reference Manual Volume IV-g: microMIPS™